Here is Projects list. We are not stick only these list of projects but also we accept any other papers. Your ideas are always Welcome.
1.
Design and implementation of high-performance
high-valency ling adders
2.
Design and Analysis of Reversible Ripple, Prefix
and Prefix-Ripple Hybrid Adder
3. Improvement
of Wallace multipliers using parallel prefix adders
4.
FPGA-Specific Arithmetic Optimizations of
Short-Latency Adders
5. Architecture
of adders based on speed, area and power dissipation
6. A developed
adding and latency reducing method for high speed pipelined adders
7. On Modulo
2^n+1 Adder Design
8. Implementation
of 32-bit Ling and Jackson adders
9. Design of
optimal final adder for parallel multiplier
10. Design and
characterization of parallel prefix adders using
FPGAs
11. FPGA
implementation of binary coded decimal digit adders
and multipliers
12. Design of low
power high speed VLSI adder subsystem
13. Low error bit
width reduction for structural adders of
FIR filters
14. Design of
Linear Phase FIR Filters With High Probability of Achieving Minimum Number of Adders
15. Multi-operand
Redundant Adders on FPGAs
16. Design and
implementation of low power digital FIR filter based on low power multipliers
and adders on xilinx FPGA
17. VLSI
implementation of adders for
high speed ALU
18. Design of
64-bit low power parallel prefix VLSI adder for high speed arithmetic circuits
19. Design of 4
bit low power carry select adder
20. A very fast
and low power carry select adder circuit
21. Evaluation of
power efficient adder and multiplier circuits for FPGA based DSP applications
22. ASIC design
of reversible full adder circuits
23. A new
reversible design of BCD adder
24. A Low Cost
circuit level fault detection technique to Full Adder design
25. A new
approach for high performance and efficient design of CORDIC processor
26. A low power
programmable FIR filter using sharing multiplication technique
27. Design and
implementation of a high performance multiplier using HDL
28. High Speed
Modified Booth Encoder Multiplier for
Signed and Unsigned Numbers
29. Design and
implementation of two variable multiplier using
KCM and Vedic Mathematics
30. Design of
low-power and high performance radix-4 multiplier
